/*
 * Copyright 2024 ywcai
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

`include "defines.v"
`timescale 1ns/1ps

module make_pctarget(
	input	wire[`MemAddrBus]	pc_i,
	input	wire[`RegDataBus]	offset_i,

	output	wire[`MemAddrBus]	pc_target_o
	);
   
	assign pc_target_o = pc_i + offset_i[`ADDR_MSB:0];

endmodule
